Sunday, July 26, 2015

GPS Disciplined Oscillator User Guide

This is the permanent home for the GPS Disciplined Oscillator User Guide. More information can also be found at the Hackaday.io project page.

Versions:
  • v1.0 - original prototype design
  • v1.1 - Change from an ATMega328p controller to an ATTiny4313
  • v1.2.1 - Add a buck converter to replace the LDO regulator
  • v1.4 - Numerous power bus cleanup and stabilization fixes, the return of the LDO, and change the buffer amp to an inverting compression amp to increase DAC granularity.
  • v1.5.3 - Redesigned to fit in new extruded aluminum enclosure
  • v1.6.2 - OH300 variant
  • v1.7.2 - Change to a 20 MHz oscillator, 5 volt logic system. Derive output from controller timer, use 2 DIP switches to select output frequency from four options.
  • v1.7 - OH300 variant for 1.7.x
  • v2.2 - Go back to a 10 MHz oscillator, but add a phase comparator system, a separate high precision LDO for the DAC reference, an extra LC filter on the 3.3v supply output, remove the output frequency selection infrastructure, switch to an ATTiny841 controller, remove the battery clip and add a mini-DIN 4 diagnostic connector on the back panel.
  • v2.2.1 - DOT050V variant for v2.2.
  • v2.4.1 - Add JFET to increase phase detector voltage linearity. Add pi network to one output for +13 dBm sine. Change ext ant jack to board-mount SMA.
  • v2.5.1 - DOT050V variant of 2.4.1.
The GPS Disciplined Oscillator board is an extremely accurate source of a 10 MHz signal. The signal is available either as a 5V square wave or a +13 dBm sine wave (both with 50Ω impedance). This can be used as a calibration source or an external reference for any number of different pieces of lab equipment, or can even be used as a master clock for microcontroller projects that require extreme clock precision.

At the heart of the board is a VCTCXO that has an inherent short-term stability of ±1 ppb or a VCOCXO that has a short-term stability of ±100 ppt. However, the fixed frequency variants of these oscillators only have an initial accuracy of ±1 ppm. For applications where both the accuracy and stability are important, using a "steerable" oscillator with feedback from an external reference is preferable. GPS offers an extremely accurate and cost effective synchronization source, however typically only a 1 PPS signal is available (though that 1 PPS signal is within ±10 ppb). This board uses a microcontroller to observe both the oscillator output and the PPS signal and tune the oscillator so that it emits as closely to an exact 10 MHz as can be measured. In addition, there is a phase discriminator circuit that will give additional phase correction information to the controller, approximately at nanosecond resolution.

The power supply should be 5 volts DC and capable of supplying at least 1W for the TCXO variant and 5W for the OCXO variant. There are three LEDs on the bottom right corner of the board. They are labeled FIX, 0 and 1. The FIX LED comes straight from the GPS receiver. At startup, or if the fix is lost, it will blink once per second. When a fix is (re)acquired, it will begin to blink once every 15 seconds. The 0 and 1 LEDs will blink back and forth when the GPS fix is lost. If they're not blinking, then they form a binary number 0-3, which correspond to the PLL operating mode. 0 (no LEDs on) corresponds to the coarse tuning mode, 1 (LED 0 on, 1 off) the fine tuning mode and 2 (LED 1 on, 0 off) the "run" mode. In general, with good GPS reception, the unit should arrive at the run mode within an hour. It's in this mode that you should expect to achieve the expected performance. If the GPS fix is lost, the unit will free-run until it returns, then re-enter the coarse, fine and then run modes.

There are two independent output ports. Each outputs a separate copy of the same signal. One output is a sine wave with approximately +13 dBm level, the other is a 5 volt, 50% duty cycle square wave. This output can be fed, if desired, into 50 ohm coax.

The GPS module has an internal patch antenna, but there is an external antenna connector on the board if you need to connect an external antenna. Depending on your board version, it is either a U.FL connector or an SMA edge-mount connector. The antenna will be fed 3.3 volts at up to 25 mA. In order for the external antenna to be recognized, it must present a DC load of at least 200 Ω. If you buy your unit in an enclosure, the internal patch antenna will not be useful because of the shielding provided by the enclosure, so an external antenna is required.

The operating temperature range of the board is 0-70°C. Rapid temperature swings should be avoided for best frequency stability.

If you need to upgrade the firmware, there is a 6 pin AVR ISP connector on the edge of the board. For board versions before v1.7, the programmer must be able to program at 3.3 volts with the target powered. DO NOT APPLY 5 VOLTS TO THE PROGRAMMING PORT OR PROGRAM WITH 5V LEVELS! You will likely irreparably damage either the oscillator or the GPS module (the two most expensive components). Programming the OCXO variant must take place with the board powered with its normal power supply, as most programmers will not be able to supply sufficient power for the oscillator to operate normally. For versions 1.7 and beyond, you should use 5 volt programming, but the recommended method is to always power the board with its own power supply and use a programmer configured for target power.

There is a mni-DIN 4 pin diagnostic connector on the board. It has a ground pin, two 3.3v async serial lines and a PPS output. One of the serial lines is the transmit data pin from the GPS module, the other is the transmit data pin from the controller. The controller transmit pin is tied to the GPS module receive pin (and vice-versa) as well as the diagnostic port. With normal firmware, the controller will not transmit anything. The GPS data will be at 9600 bps and can be tapped for other purposes, if desired. The PPS output is buffered. The rising edge will, in principle, be synchronized to the GPS second, but the output buffer will introduce a few ns of latency. It's recommended, therefore, that this be only used as a frequency standard, rather than a timing output (the latency should be fixed length given a fixed load).

When the "run" lock indication is present on the LEDs, you can expect the Allan deviation for the DOT050V variant for all tau to be 1e-9 or better. Typical performance levels are between 6E-11 and 9E-11 for tau 6E-1 through 3E+3, and then proceeding downwards from there. No representation or assertion is made about the phase of the output relative to GPS, only the frequency. You can expect the OH300 variant to be around 7E-12 for tau 1E0, rising to around 2E-11 at tau 3E+3 and then proceeding downwards from there.

After power is applied, it may take the GPS receiver up to a minute (assuming good GPS reception) to obtain a 3D fix (as indicated by the change from once-per-second blinking of the FIX LED to once every 15 seconds, plus the 0 and 1 LEDs changing from blinking back and forth to extinguishing). Once a GPS lock is indicated, it will take anywhere from 20 to 40 minutes for the coarse mode to bring the frequency within approximately 1E-9. The fine mode should take a few minutes more, and then the run mode should turn on and stay. If the GPS lock is lost, the unit will free-run until GPS is re-acquired, and then the startup process will repeat (but should be much faster, as the free-running frequency should be much closer to the target).

Note that the oscillator is sensitive to movement. If you move it while it's operating, you can expect phase disturbances that the PLL will have to correct. While each output is isolated, large changes in load can do the same. After changing output connections, or jostling the unit, you should give the oscillator a few minutes to settle.

The coarse mode implements a basic FLL that attempts to get close to center as quickly as possible. Once there, the FLL is maintained until the phase drifts close to the phase discriminator center point (for a maximum of 20 minutes). The coarse PLL mode operates with a time constant of 50 seconds, and the fine PLL mode with a time constant of 200 seconds.

Theory of operation

At the heart of the system is a voltage controlled, temperature compensated crystal oscillator or oven controlled crystal oscillator running at 10 MHz. The voltage control pin has a range of 0.3-3.0 volts and swings the output frequency either ±10 ppm (for the TCXO) or ±0.4 ppb (for the OCXO). This voltage must be kept as linear, stable, and noise-free as possible. The output of the DAC is fed into a resistor divider network. The resulting transfer equation is Vout = -n*(Vin-1.65) + 1.65, where n is roughly 0.5 for the TCXO and 0.8 for the OCXO. This results in a range of 0.825 volts (DAC value 0) to 2.476 volts (DAC value 0xffff), for a tuning range of roughly 12 ppm in 200 ppt steps for the TCXO, or a range of 0.2475 volts (DAC value 0) to 3.0525 volts (DAC value 0xffff), for a tuning range of roughly 800 ppb in 15 ppt steps for the OCXO. The DAC is a 16 bit serial DAC. Its default power-up state is to output a mid-range voltage. To insure that the DAC is not accessed while the controller is being programmed, there is a pull-up resistor on the !SYNC line (which is effectively a chip-select line). This is necessary because during programming the output from the controller will be floating.

The output of the oscillator goes into a 1:4 fan-out buffer (with a loading capacitor to bring the load on the oscillator to its rated requirement of 15 pF). One of the outputs of the buffer goes into the clock input line of the ATTiny841. Another goes into the input of a divide-by-10 chip, and then to the phase discriminator. The other two are presented as outputs, after going through an impedance resistor (to absorb reflected power from impedance mismatches). One of those two has a simple pi network low-pass filter to convert the output to sine.

The phase discriminator is a 4046 PLL chip. The VCO section is disabled by pulling the INH pin high. The signal pin is fed from the 1 MHz clock from the divide-by-ten. The reference pin is fed from the GPS PPS pin. As a result, the PD3 output is a positive-going pulse anywhere between 0 and 1 µs wide. This output is fed through a Schottky diode into an RC network with a time constant of 680 ns. The result is a voltage between 0 and approximately 4 volts roughly proportional to the width of the pulse. A 10 MΩ resistor across the cap yields a discharge time constant of 6.8 ms, which insures that the cap is discharged before the next PPS pulse arrives. The output of this arrangement is fed into an ADC input pin of the controller. The PPS interrupt will cause the ADC to be read, resulting in a value between 0 and 1023 that roughly corresponds to a phase shift of -512 to +512 ns. The arrangement is not tremendously precise, but it doesn't need to be - the important part is the rate at which the phase changes, not what the absolute phase actually is. The software will lock the phase to what amounts to a totally arbitrary - but constant - value.

The ATTiny841 is directly clocked from the oscillator. Its internal timers are therefore clocked at this frequency. The ATTiny841 has an input capture capability, where the present value of the 16 bit timer can be "captured" on a rising edge of its ICP pin. This also causes a capture interrupt. The ICP pin is fed from the GPS module's PPS pin. The firmware will effectively count how many cycles of the 10 MHz oscillator output occur between each PPS rising edge. A single count delta in one seconds represents ±100 ppb, which when averaged is used by the "coarse" tuning mode to get the frequency within 1 ppb or so, which means the phase shift will be slow enough for the PLL to be able to lock without having to unwrap the swings.

The serial port of the GPS module is also connected to the controller. The controller watches for NEMA $GPGSA sentences and looks for an indication of a proper 3D fix. If the GPS is not 3D locked, then it will be ignored and the system will hold-over until it comes back.

There are four separate power supply systems. First, 5 volts comes in from the external power input. There is a TVS diode to serve as a crude over-voltage and reverse polarity protection, and a tantalum cap to act as a noise filter. This is the primary source of 5 volt power for the other power supplies. For the digital section, a 47 µH inductor provides isolation from noise imposed by the digital circuitry. From the digital 5v bus, a dedicated LDO supplies 3.3 volt power for the GPS module.

From the 5v input bus, a 3.3 volt oscillator supply is derived using either an LDO for the TCXO variant or an SC189Z buck converter for the OCXO variant. The buck converter has an extra LC added onto the output to form a pi filter to further reduce noise and ripple.

Also from the 5v input bus, a separate high precision 3.3 volt regulator supplies the reference voltage for the DAC and also the supply voltage for the compression amp and the virtual ground voltage divider.

Schematics




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